1. Field of the Invention
This invention relates to a thin film transistor (hereinafter called TFT) and a process for producing the same, particularly a TFT and a process for producing the same which are intended to improve the yield of TFT and simplify the production steps.
The TFT according to the present invention is applicable for, for example, switching transistors, etc. of an active type liquid crystal display device.
2. Related Background Art
FIG. 1 shows a schematic sectional view of TFT of the prior art in an active type liquid crystal display device.
The TFT in this Figure is prepared as follows. First, on an insulating substrate 1 made of glass, etc., a gate electrode 2 and a picture element electrode 3 are formed, and an insulating layer 4 is formed on these electrodes. Subsequently, on the insulating layer 4 is deposited a semiconductor layer and the unnecessary portion is removed by selective etching to form a semiconductor layer 5 for generating channel. Subsequently, after formation of a contact hole 6, the main electrodes 7 and 8 (here, the source electrode 7 and the drain electrode 8) are formed.
When an appropriate voltage is applied on the gate electrode 2 of the TFT thus prepared, a channel is formed in the semiconductor layer 5, wherein TFT becomes the ON-state. Accordingly, if driving voltage is applied on the source electrode 7 of the TFT, driving voltage can be applied on the picture element electrode 3 through the TFT, whereby the liquid crystal (not shown) can be driven at any desired time.
As can be apparently seen from the above description, at least 5 photolithographic steps are required for preparation of TFT of the prior art as described above. That is, they are the respective steps of forming a gate electrode 2, a picture element electrode 3, a semiconductor layer 5, a contact hole 6 and main electrodes 7 and 8. In carrying out these steps, high precision are required for alignment between the gate electrode 2 and the semiconductor layer 5 or between the semiconductor layer 5 and the main electrodes 7 and 8 as well as for dimensions thereof.
However, according to the production process in the prior art, due to the alignment errors in the respective photolithographic steps, there has been the problem that discrepancy in position and dimension of the portions superposed of the photomask surfaces having patterns is liable to occur.
Further, due to a large number of etching steps, the insulating region such as the insulating layer 4 is susceptible to damages to form pinholes therein, whereby there has been also the problem that deterioration of the characteristics of the TFT or leak at the crossed portion between the multi-layer wirings (hereinafter called cross-point) occurs to lower the yield. In the prior art example as described above, the insulating layer 4 suffers from damages in the etching step for forming the semiconductor layer 5 on the insulating layer 4 and the etching step for forming the contact hole 6 on the insulating layer 4, whereby leak occurs between the gate electrode 2 and the source electrode 7 at higher probability to lower the yield of the TFT.